The present disclosure relates in general to semiconductor device structures and their fabrication. More specifically, the present disclosure relates to the fabrication of a fin-type field effect transistor (FinFET) using a high-k and p-type work function metal first fabrication process that improves, inter alia, source/drain activation annealing and dielectric reliability annealing.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
One particularly advantageous type of MOSFET is known generally as a fin-type field effect transistor (FinFET). FIG. 1A depicts a three-dimensional view of an exemplary FinFET 100, which includes a shallow trench isolation (STI) region 104 for isolation of active areas from one another. The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional field effect transistor. FinFET 100 includes a semiconductor substrate 102, local STI region 104, a fin 106, and a gate 114 having a gate oxide layer (not shown) between the gate and the fin, configured and arranged as shown. Fin 106 includes a source region 108, a drain region 110 and a channel region 112, wherein gate 114 extends over the top and sides of channel region 112. For ease of illustration, a single fin is shown in FIG. 1. In practice, FinFET devices are fabricated having multiple fins formed on local STI region 104 and substrate 102. Substrate 102 may be silicon, and local STI region 104 may be an oxide (e.g., SiO2). Fin 106 may be silicon. Gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1). In contrast to a planar MOSFET, however, source 108, drain 110 and channel 112 are built as a three-dimensional bar on top of local STI region 104 and semiconductor substrate 102. The three-dimensional bar is the aforementioned “fin 106,” which serves as the body of the device. The gate electrode is then wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. The source and drain regions are the portions of the fin on either side of the channel that are not under the gate electrode. The source and drain regions may be suitably doped to produce the desired FET polarity, as is known in the art. The dimensions of the fin establish the effective channel length for the transistor.
Transistors have been made with silicon dioxide gate dielectrics and poly-silicon gate conductors for decades. However, as transistors have decreased in size, gate dielectric thickness has scaled below 2 nanometers, which increases tunneling leakage currents and power consumption and reduces device reliability. Replacing the silicon dioxide gate dielectric with a high-k material having a high dielectric constant (k) in comparison to silicon dioxide allows increases gate capacitance without the associated leakage effects. Suitable high-k materials include hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, typically deposited using atomic layer deposition.
Replacing the silicon dioxide gate dielectric with another material adds complexity to the fabrication process. For example, implementing the gate dielectric based on high-k oxides of hafnium requires the poly-silicon gate material to be replaced with a metal that interfaces better with the high-k dielectric. Accordingly, the poly-silicon gate must be etched out and replaced with metal. The metal-gate may be formed before or after the source and drain regions. Forming the metal gate last (i.e., after formation of the source and drain regions) is known generally as a replacement metal gate (RMG) process flow.
Known process flows for the metal gate formation involves independently optimized complex stacks of thin work-function metals topped by a bulk conductor layer. Additionally, a typical fabrication process flow includes multiple annealing operations, including, for example, a high-k post-deposition anneal (PDA), a high temperature anneal applied to the high-k dielectric to improve reliability, and a high temperature source drain anneal applied to the doped source and drain regions to activate these regions.